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U2102B
Multifunction Timer
Description
The monolithic integrated bipolar circuit U2102B is a MOSFET or IGBT control circuit which allows the realization of an extremely wide range of timer and dimmer functions. The integrated current monitoring function additionally permits the power switch to be reliably protected without an additional fuse.
Features
D Integrated reverse phase control D Two- or three-wire applications D Mode selection:
- Zero-voltage switch with static output - Two-stage reverse phase control with switch-off - Two-stage reverse phase control
D Adjustable and retriggerable tracking time D External window adjustment for sensor input D Enable input for triggering
Applications
D Motion detectors D Time-delay relays D Dimmers D Reverse phase controls D Timers
D Current monitoring:
- High-speed short-circuit monitoring with output - High-current monitoring with integrating buffer
D Integrated chip temperature monitoring
Block Diagram
1 VRef 2 3 4 Voltage monitoring 16 Synchronization 15 Voltage limitation Control RC oscillator Divider logic 6 13
Reverse phase control
5
Push pull
14
12 Programing Current monitoring 11
Triggering with buffers 7 8 9
Temperature monitoring
Test logic 10
Figure 1. Block diagram
Rev. A2, 09-Nov-99
1 (15)
U2102B
Ordering Information
Extended Type Number U2102B-x U2102B-xFP U2102B-xFPG3 Package DIP16 SO16 SO16 Remarks Tube Tube Taped and reeled
Pin Description
VRef 1 CRamp 2 RRamp 3 Control 4 16 Sync 15 +VS 14 VO 13 GND Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol VRef CRamp RRamp Control Osc Prog. EN Trigger V9 Test II Ioff GND VO + VS Sync Function Reference voltage 5 V Ramp, capacitance Current setting for ramp Control voltage RC oscillator Tri-state programming Enable input Trigger input (window) Window adjustment Test output Input current monitoring Fast output current monitoring Ground Output voltage Supply voltage Synchronization input
U2102B
Osc 5 Prog. 6 EN 7 Trigger 8
Figure 2. Pinning
12 11
Ioff II
10 Test 9 V9
2 (15)
Rev. A2, 09-Nov-99
1
VRef 1k
Clock
Clock generator
Synchronization
16 68 k +Vs
230 V
W
Voltage limitation Push pull
W
Load
R2
1M
W W W
10 nF C3
2
Ramp
15 14
47 F/25 V C1 IGBT RG
m
22 k
820 k R3
W
3 +
Reverse Phase Temp monitoring GND 13 QQ RS Control POR Current monitoring Buffer 120 ms Clock Test logic Clock 10 + - 100 mV Test mode Enable
0.55 x VRef + 0.2 V 9
Rsh
Control
4
Control
100k
-
5 CRef 1F
12
100
W
1k
RC oscillator
Divider
m
C2 220 nF VRef + VS GND 6 VRef Stat. ZVS Voltage monitoring
W
- +
500 mV 11 1 nF
logic
+ VS 2 stage / out GND 2 stage
0.02xVRef
Enable
7
0.1/0.4/ 0.5 x VRef
Buffer (spikefilter)
V Ref
+ Trigger signal 8 - Trigger window + -
0.45 x VRef - 0.2 x V9
Window adjustment
9 NTC
X
Rev. A2, 09-Nov-99
Figure 3. Block diagram with typical circuit for dc loads
R1 33 k
W /2W
Vmains
U2102B
3 (15)
U2102B
Power Supply, Synchronization Pins 15 and 16
The voltage limitation circuit contained in the U2102B enables simple power supply via a dropping resistor R1. In the case of dc loads, practically all the supply current flows into Pin 16 (the pull down resistor at Pin 16 is necessary in order to guarantee reliable synchronization) and is supplied via an internal diode to Pin 15, where the resultant supply voltage is limited and smoothed by C1. As a result, the rectified and divided line voltage appears at Pin 16, where the amplitude is limited. The power supply for the circuit can be realized in all modes for dc loads as shown in figure 3. The voltage at Pin 16 is used to synchronize the circuit with the mains and generate the system clock required for the buffers. The circuit detects a "zero crossing" when the voltage at Pin 16 falls below an internal threshold of approximately 8 V.
Vmains R1=Rsync Sync. 16
+VS 15 Voltage limitation Push pull 14 Temp. monit. GND 13 C1
Load
IGBT RG Rsh
Figure 4. Power supply for dc loads (R1 is identical with Rsync)
R1 is calculated here as follows: V Nmin -V S R 1max 0.85 (1) I tot
+
Itot ISmax Ix
=
=
ISmax + Ix Max. current consumption of the IC Current consumption of the external components
where: VNmin = VS = Vmains - 15% Supply voltage
=
4 (15)
Rev. A2, 09-Nov-99
U2102B
In the case of ac loads, it is necessary to make a distinction for power supply purposes between the individual operating modes. In reverse phase control mode, figure 4, Pin 15 must be additionally supplied with power via a dropping resistor, since no current flows in Pin 16 when the power switch is switched on. Here, the dropping resistor, R1, is connected before the rectifier bridge and therefore has only one mains half-wave. R1 is then calculated as follows: R 1max
+ 0.85
V Nmin -V S 2 I tot
Load Rsync Sync. 16 R1 +VS 15 Voltage limitation Push pull 14 Temp. monit. GND 13 C1 IGBT RG Rsh D1
Vmains
Figure 5. Power supply in reverse phase control mode for ac loads
In two-wire systems, the additional power supply at Pin 15 is not possible (see figure 4, by omitting R1 and Diode D1). In this case, the resistor Rsync is identical with R1 and should be as low as the power dissipation allows it. A sufficiently large residual phase angle must remain in this case in order to guarantee the device supply.
The power supply is simplified if the device is operated as a static zero-voltage switch for ac loads (see figure 5). All delay times are twice as long here, since synchronization of the module is tapped before the rectifier bridge.
Load R1= Rsync Sync. 16
Vmains
+VS 15 Voltage limitation Push pull 14 Temp. monit. GND 13 C1 IGBT RG Rsh
Figure 6. Power supply as static zero voltage switch for ac loads
Rev. A2, 09-Nov-99
5 (15)
U2102B
Voltage Monitoring
While the operating voltage is being built up or reduced, uncontrolled conditions or output pulses of insufficient amplitude are being suppressed by the internal monitoring circuit. All latches in the circuit, the divider and the control logic are reset. When the supply voltage is applied, the enable threshold (clamp voltage) of approximately 16 V must be reached so that the circuit is enabled. The circuit is reset at approximately 11 V if the supply voltage breaks down. A further threshold is activated in reverse phase control mode. If the supply voltage breaks down here after enabling of the circuit, the output stage is switched off at approximately 12.5 V, while the other parts of the circuit are not affected. The output stage can then be switched on again only in the following halfwave. As a result, the residual phase angle remains just large enough, (e.g., in two-wire systems), so that the circuit can still be properly supplied with power. In all operating modes, a single operating cycle is started after the supply voltage is applied, independently of the trigger inputs, in order to immediately demonstrate the overall function.
Reverse Phase Control, Pins 2, 3, 4
In the case of normal phase controls, e.g., with a triac, the load current is switched ON only at a certain phase angle after the zero crossing of the mains voltage. In the following zero crossing of the current, the triac gets extinguished (switched-off) automatically. Reverse phase control differs from this in that the load current is always switched-on by a semiconductor switch (e.g., IBGT) at the zero crossing of the mains voltage and then switched back off again after a certain phase angle a. This has the advantage that the load current always rises with the mains voltage in a defined manner and thus keeps the required interference suppression to a minimum. The charging current for the capacitor C3 at Pin 2 is set with the resistor R3 at Pin 3. When the synchronization circuit recognizes a zero crossing, an increased charging current I2 4 I3 is enabled which then charges C3 up to 0.45 V. The output stage is switched-on at this value and the charging current for C3 is reduced to I2 = I3. Since the actual zero crossing of the supply voltage occurs later than recognized by the circuit, the load current starts to flow quite close to the exact zero crossing of the supply voltage. While the output stage is switched-on C3 is charged until the control voltage, set externally at Pin 4, is reached. When this condition is reached, the output stage is switched off and C3 is charged again with the increased current (I2 = 4 I3) to V2 5.5 V. The charging current is switched off at this point and C3 is discharged internally. The whole process then starts again when the circuit recognizes another zero crossing (see figure 6).
[
[
Chip Temperature Monitoring
The circuit possesses an integrated chip temperature monitoring circuit which disables the output stage when a temperature of approximately 140C is reached. The circuit is enabled again only after cooling down and additionally switched "off and on" of the operating voltage.
[
Vmains t
V2 1.1 VRef V4 0.09 VRef t V14
t
Figure 7. Signal characteristics of reverse phase control
6 (15)
Rev. A2, 09-Nov-99
U2102B
Programing, Pin 6
Three operating modes can be programed with the tristate input Pin 6: This threshold is approximately 2 V in switched-off condition and also during the second current flow angle, a, in two-stage reverse phase control mode. Otherwise, the blocking-or switch-off threshold is 0.5 V. The input Pin 8 is designed as a window discriminator, its window is set at Pin 9. The minimum window of approximately 250 mV is set with V9 = V13, and the maximum window of approximately 1.25 V with V9 = Vl. The window discriminator is in the OFF state when the voltage at Pin 8 lies within the window set at Pin 9. If a resistor divider with an NTC resistor is connected to Pin 9, for example, it is possible to compensate for the temperature dependence of the IR sensor, i.e. the range is made independent of temperature. Noise suppression for tON = 40 ms guarantees that there is no peak noise signals at the inputs which could trigger the circuit. Equally, renewed triggering is prevented for tOFF = 640 ms after load switch-off in order to avoid any self interference.
D Zero-voltage switch (ZVS)with static output
(V6 = V1 = VRef): The reverse phase control is inactive here. The output stage is statically switched-on after triggering by the timer and switched-off again after the running down of the time (at the zero crossing of the supply voltage in each case). This operating mode is not possible in two-wire systems.
D Two-stage reverse phase control with switch-off
( V6 = V15 = VS): The maximum current flow angle, amax, is set when the timer has enabled the output stage. Switchover to the phase angle a, which can be set arbitrarily at Pin 4, takes place after expiry of 3/4 of the tracking time set at Pin 5. The output stage switches off after expiry of the whole tracking time.
D Two-stage reverse phase control ( V6 = V13 = GND):
The output stage switches to the maximum current flow angle, amax, (adjustable) if the trigger condition for both inputs (Pins 7, 8) is satisfied. Switchover to the current flow angle, a, set at Pin 4 takes place after expiry of 3/4 of the tracking time set at Pin 5. The whole process is repeated from the beginning again if renewed triggering takes place at Pin 8. The lamp is switched-off in the following half-wave of the mains voltage if the trigger condition at Pin 7 disappears. In this mode, the output stage is switched-on even if only Pin 7 is in the ON state. The current flow angle is then determined by V4 (e.g., house no. illumination, twilight switch).
V7 VRef ON 0.5 VRef Hysteresis 0.1/0.4 VRef OFF 0
Figure 8. Trigger condition Pin 7
Trigger Inputs, Pins 7 and 8
The trigger condition of the timer is determined by the two inputs Pins 7 and 8. A Light Dependent Resistor ( LDR) can be connected to Pin 7, for example, and an IR sensor to Pin 8. Both inputs must be in the ON state to initiate triggering, since they are equal and AND-gated. In the operating mode "2-stage reverse phase control", the output stage can additionally be switched-on and switched-off by Pin 7 alone and independently of the timer. The enable input Pin 7 is implemented as a comparator with hysteresis. The enable threshold is approximately 2.5 V. The blocking threshold is switched by the control logic in order to avoid faults as a result of load switching. Rev. A2, 09-Nov-99 V8 VRef ON 0.5 VRef 0.05 VRef + 0.2 V9 0.05 VRef + 0.2 V9 ON 0
Figure 9. Trigger condition Pin 8
OFF
7 (15)
U2102B
RC Oscillator, Pin 5
An internal RC oscillator with following divider stage 1:211 permits a very long and reproducible tracking time. The RC values for a certain tracking time, tt, are calculated as follows: R 2 (kW) C 2 (mF)
Current Monitoring, Pins 11 and 12
The current monitoring circuit integrated in the U2102B represents a double electronic fuse. The circuit measures the current flowing through the power switch by way of the voltage drop across the shunt resistor Rsh. This voltage is supplied to Pin 11. If this voltage exceeds a value of 500 mV because of a high load current (e.g., shortcircuit), the switch-off latch is set and the switching output Pin 11 closes immediately. Pin 11 can be connected to the gate via a resistor or network, depending on load conditions, thus allowing the switch-off behavior to be adapted to the respective requirements. The shortcircuit current is reduced to a problem-free value by this procedure. There is a second threshold at 100 mV. The output stage is disabled if the voltage at Pin 11 exceeds this value and if it reaches this value for 120 ms in every half-wave without exceeding the switch-off threshold of 500 mV. Since high voltage peaks would be caused by switching off due to the line and leakage inductances, the output stage is not switched-off immediately but is simply not enabled in the next half-wave. The circuit is designed so that it also switches off in the case of changing overcurrents which do not occur in every half-wave. But in this case the switch-off time is larger.
+ 1.4 + 1.4
t t(s) 10 3 2048 C 2 (mF) t t(s) 10 3 2048 R 2 (kW)
In reverse phase control mode, switchover from maximum current flow angle to the value set at Pin 4 takes place after expiry of 3/4 of the total tracking time tt.
Absolute Maximum Ratings
Reference point Pin 13, unless otherwise specified Parameters Power supply Current t < 10 Synchronization Input current Symbol Pin 15 IS is II ii - IRef Value 20 60 20 60 10 10 60 1 8 0.2 1 20 0 to V1 0 to V15 - 40 to + 125 + 125 - 10 to + 100 Unit mA mA mA mA mA mA mA mA mA mA mA mA V V C C C
ms ms
t 10 Reference voltage source Output current Push-pull output stage Output current t 2 ms Input currents
v v
Pin 16
Pin 1 Pin 14 Pin 14 Pin 2 Pin 2 Pin 3 Pin 10 Pin 12 Pins 4, 5, 7, 8, 9 and 11 Pins 6 and 12
"I "i "
O o
Input voltages Storage temperature range Junction temperature Ambient temperature
-II II -II II II VI VI Tstg Tj Tamb
8 (15)
Rev. A2, 09-Nov-99
U2102B
Thermal Resistance
Junction ambient Parameters DIP 16 SO 16 on PC board SO 16 on ceramic Symbol RthJA RthJA RthJA Value 120 180 100 Unit K/W K/W K/W
Electrical Characteristics
VS = 15.0 V, fmains = 50 Hz, Tamb = 25C, reference point Pin 13, unless otherwise specified Parameters Supply voltage limitation Current consumption Voltage monitoring Switch-on threshold Switch-off threshold Undervoltage threshold Reference voltage Synchronization Voltage limitation Input current Zero crossing switch-on threshold Zero crossing switch-off threshold Reverse phase control Ramp current setting Input current Input voltage Ramp Charging current 1 Charging current 2 Discharge impedance Switch-on threshold, output stage Discharge threshold voltage Control voltage Input voltage Input current Programing, tri state input Input current Operating mode: Static zero-voltage switch 2-stage reverse phase control with switch-off it h ff 2-stage reverse phase control RC oscillator Input current Upper threshold Lower threshold Discharge impedance Test Conditions / Pin Symbol IS = 2 mA Pin 15 VS VS IS = 5 mA VS = 15 V Pin 15 IS Pin 15 VSON VSOFF V15 - I1 = 0 to 5 mA Pin 1 VRef I16 = 2 mA V16 = 0 V Pin 16-15 Pin 16 Pin 16 Pin 16 Pin 3 Vlimit - II VTON VTOFF Min. 15 15.2 Typ. Max. 17 17.2 2 16.5 11.6 13.3 5.25 Unit V V mA V V V V
14.8 10.4 11.7 4.75
11 12.5 5 0.8 100 7.7 8.3
7.3 7.9
8.1 8.7
mA
V V
V
I3 = - 10 I3 = - 10
mA mA
- II V3 Pin 2 - Ich1 - Ich2 Rdis VTON Vdis
4.7 9 37 410
5 10 40 1 450 600
50 5.3 11 43 490
mA
V
Pin 2-1 Pin 4 V13 V13
kW mV mV V nA
mA mA
vV vV vV vV
4 6
l
Pin 6
15
"I "I
VI VI VI
0
I I
VRef 500 1
mA
V V nA V V kW
1 VRef +1 0
I
VRef+0 3 +0.3
VS 0.3 500 4.4 1.1
V13
vV
Pin 5
5 < 3.6 V
VTU VTL Rdis
"I
3.6 0.9
4 1 1
Rev. A2, 09-Nov-99
9 (15)
U2102B
Parameters Window discriminator Input current Upper threshold Lower threshold Input current window adjustment Minimum window: Lower threshold Upper threshold Maximum window: Lower threshold Upper threshold Enable Schmitt trigger Input current Enable threshold Blocking threshold: Output stage OFF Output stage ON, except in the case of two-stage reverse phase control in second stage (a) Threshold for test mode Current monitoring Input current Switch-off threshold 1 Switch-off threshold 2 Switching output Leakage current Saturation voltage Test Conditions / Pin 0V Symbol Min. Typ. Max. Unit nA V V nA V V V V nA V V V
vV vV
8
Pin 8 l Pins 8 and 9
1
"I "I
i
0 V V9 V9 = V13
v vV
VTU VTL
i
0.55 0.45
@V @V
Ref + (0.2 Ref - (0.2
@V ) @V )
9 9
500
Pin 9 Pin 8
500 2.05 2.55 1.1 3.4 2.75 3.75 1.25 3.75 2.45 2.95 1.4 4.1 500 2.7 2.2 0.55
VTL1 VTU1 V9 = V1 Pin 8 VTL2 VTU2 0V
vV vV
7
Pin 7
l
"I
i
VT VT VT
2.3 1.8 0.45
2.5 2 0.5
VT 0V
85
100
115 500 120 550 1 1.0 1.2 2.4 1.2
mV nA mV mV
vV vV
11
Pin 11
1
VT1 VT2
"I
i
80 450
100 500
V11 < 450 mV, V12 V11 > 550 mV I12 = 0.5 mA I12 = 10 mA
v
Pin 12 V15
Ilkg VSat VSat - VSat VSatL -IO IO 50 50
mA
V V V V mA mA
Push-pull output stage Upper saturation voltage, ON state Lower saturation voltage, OFF state Output current
I14 = - 10 mA Pins 14 and 15 I14 = 10 mA Pin 14 ON state OFF state Pin 14
10 (15)
Rev. A2, 09-Nov-99
U2102B
Applications
Vmains 230 V Load GND
X
Rsh 1 kW
1 nF
22 kW/2 W R1 1N4007 Rsync 220 kW C1 47 mF/ 25 V
IGBT
100 W
RG
VRef
NTC
100 kW VS 16 15
14
13
12
11
10
9
U2102B
1 C3 10 nF
2
3
4 R3 820 kW Control
5
6
7
8
VS GND 220 nF Enable
100 kW 1 MW R2 22 kW
C2 CRef 1 mF
Trigger signal
Figure 10. House number or staircase illumination for ac loads House number illumination: V6 = V13 Staircase illumination: V6 = V15
Rev. A2, 09-Nov-99
11 (15)
U2102B
Vmains 230 V Load GND
X
Rsh 1 kW
1 nF
IGBT
100 W
R1 = Rsync 18 kW/2 W 1N4007
68 kW C1 47 mF/25 V VS 16 15 14
RG
VRef
NTC
13
12
11
10
9
U2102B
1 C3 22 nF 2 3 R3 750 kW 4 5 6 7 8
C2 220 nF 1 MW 22 kW
Enable
Trigger signal R2 CRef 1 mF
Figure 11. Zero voltage switch mode for ac loads
12 (15)
Rev. A2, 09-Nov-99
U2102B
Vmains 230 V Load
X
Rsh 1 kW R1 22 kW/2 W 1N4007 C1 47 mF/ 25 V RG
1 nF
IGBT
100 W VS
Rsync 220 kW
100 kW VS 16 15
100 kW
14
13
12
11
10
9
U2102B
1 C3 10 nF
2
3
4
5
6
7
8
100 kW
100 kW
R3 VS 1 MW Control 100 kW CRef 1 mF
Figure 12. Reverse phase control for ac loads
Rev. A2, 09-Nov-99
13 (15)
U2102B
Package Information
Package DIP16
Dimensions in mm
20.0 max 7.82 7.42
4.8 max 6.4 max 0.5 min 3.3 1.64 1.44 Alternative 16 0.58 0.48 17.78 0.39 max 9.75 8.15
2.54
9
technical drawings according to DIN specifications
1
8
Package SO16
Dimensions in mm
10.0 9.85 5.2 4.8 3.7
1.4 0.4 1.27 8.89 16 9 0.25 0.10 0.2 3.8 6.15 5.85
technical drawings according to DIN specifications
1
8
14 (15)
Rev. A2, 09-Nov-99
U2102B
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances ( ODSs). The Montreal Protocol ( 1987) and its London Amendments ( 1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2 . Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency ( EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C ( transitional substances ) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify TEMIC Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 ( 0 ) 7131 67 2594, Fax number: 49 ( 0 ) 7131 67 2423
Rev. A2, 09-Nov-99
15 (15)

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